1. Field of the Invention
The present invention relates to an improvement of spread spectrum modulation/demodulation system, particularly to so-called "synchronized spread spectrum system". Spread spectrum (SS) communication system is superior to others in noise durability, and capable of transmitting intelligence with less electric power. Therefore, this system is now expected as a prospective communication means from the view point of effective use of radio wave.
However, the neck engineering in the SS communication system is the complicated circuit constitution of the receiver that is required for reproducing the spread code (i.e. Pseudo-Noise (PN) code) which is spread when transmitted from the transmitter. The synchronized spread spectrum system has been developed as a means for simplifying the reproduction of the spread code in the receiver while maintaining the characteristics of the SS communication system.
2. Description of the Related Art:
In the SS communication, capturing the synchronous time and holding the synchronous condition are both necessary techniques. And, various methods have been proposed and practiced.
One example of the synchronous SS modulation/demodulation system will be explained with reference to FIGS. 14 through 18. FIG. 14 shows a transmitter, and FIG. 15 shows a receiver.
In FIG. 14, an oscillator 649 supplies a carrier Fi(t) to one input terminal of an angle modulator 609. A data signal d(t) is supplied from an input terminal In10 to the other input terminal of the angle modulator 609. The angle modulator 609 produces an angle-modulated signal fi(t), for example, by the phase shift keying (PSK).
The carrier Fi(t) is also supplied to a divided-by-N.sub.1 circuit 625, through which the frequency of the carrier Fi(t) is divided into 1/N.sub.1. This divided signal is fed to a spread code generator (PNG) 648 as a clock signal thereof. The PNG 648 generates a spread code P(t) in response to this clock signal, and sends it to a mixer 610.
The mixer 610 carries out a spread spectrum (SS) modulation by multiplying the angle-modulated signal fi(t) with the spread code P(t). An output fi(t)*P(t) of the mixer 610 is supplied to a BPF 611 and outputted from an output terminal Out10.
In FIG. 15, received SS modulation signal is inputted from an input terminal In11 to a BPF 612, in which unnecessary band components are removed. After that, the signal is sent to an automatic gain control (AGC) 602. This AGC 602 is necessary for adjusting a signal into a predetermined level suitable for a later described synchronous time detection. The SS modulation signal is amplified into a predetermined level in this AGC 602. An output of the AGC 602 is fed separately to a mixer 603 and to a sync capture circuit 636 of a delayed lock loop (DLL) type.
The mixer 603 multiplies the SS modulated signal with a spread code supplied from a PNG 647 so as to carry out the despreading operation. A voltage-controlled oscillator (VCO) 621 supplies a clock signal to the PNG 647. This clock signal is set slightly higher than that in the synchronous condition. The sliding correlation and the despreading demodulation are carried out sequentially.
Here, the sliding correlation is one of technique for catching up the spread code so as to establish the synchronous condition. First of all, the spread code clock of the receiver is slightly changed from that of the transmitter. For example, the spread code clock of the transmitter is 1 MHz and that of the receiver is 1.1 MHz. Both clocks coincide with each other every 909 .mu.s. However, phases of both codes are not always the same. That is, mutual phase slides.
When the clock phase and the code phase are both identical, the demodulation signal increases abruptly. Therefore, by returning the clock signal frequency of the receiver to the regular value, the normal despreading operation is stably carried out after this time.
The mixer 603 outputs a despreading signal P(t)*.rho.(t)*fi(t) to mixers 604 and 695 in a carrier reproduction circuit 650, as a result of multiplication of SS modulated signal P(t)*fi(t) and the spread code .rho.(t). A VCO 622 is an oscillator which follows the carrier Fi(t) of the oscillator 649. An output of the VCO 622 is supplied directly to the mixer 604, and on the other hand through a phase shifter 623 to the mixer 605. The phase shifter 623 gives a signal a phase difference of .pi./2.
These mixers 604, 605 multiply thus supplied VCO values with the output of the mixer 603. Outputs of these mixers 604, 605 are fed to an LPF 617 and an LPF 618, respectively, and multiplied with each other in a mixer 606. An output of the mixer 606 is supplied to a loop filter (LF) 624. As a result, the LF 624 generates an average error between the VCO 622 and the angle-modulated signal. In response to this average error, the VCO 622 is controlled so that the VCO 622 follows the angle-modulated signal.
In this manner, the carrier is reproduced through the VCO 622. With this function, the mixer 604 serves as a synchronous time detector with respect to the angle-modulated signal. Its output is fed to the LPF 617 and outputted from an output terminal Out11, and also fed to a threshold level detector 634 as a detection signal for detecting the synchronous time of the spread code which will be described later.
Next, the sync capture operation is explained. The SS modulation signal inputted through the BPF 612 and the AGC 602 is supplied to the DLL-type sync capture circuit 636. FIG. 16 shows the detailed construction of the DLL-type sync capture circuit 636. In FIG. 16, the SS modulated signal inputted through an input terminal In12 is added to mixers 607 and 608. A spread code P(t-.DELTA.t), whose phase is advanced with respect to the regular spread code P(t) by 1 bit of the code, and a spread code P(t+.DELTA.t), whose phase is delayed with respect to the regular spread code P(t) by 1 bit of the code are supplied to these mixers 607, 608 through input terminals In13 and In14.
Accordingly, at the time when the spread code is reproduced, an output of each mixer 607 or 608 becomes an angle-modulated signal fi(t) as a result of the despreading operation of the SS modulation signal. The maximum values are obtained at the points where the phase of the spreading code is offset by .+-.1 bit. These two outputs are fed through BPF 613, 614 to absolute-value circuits 638, 639.
In these absolute-value circuits 638, 639, the envelope of signal is detected. A subtraction circuit 640 generates a difference of output values of these two absolute-value circuits 638, 639. An output of the subtraction circuit 640 is supplied to an LF 628 and outputted through an output terminal Out12.
This output is inputted into the adder 642, and fed back to the VCO 621 so as to control this VCO 621 with the difference value of the subtraction circuit 640. The control characteristics of this control loop is shown in FIG. 17, an abscissa of which represents a phase of the spread code generated in the PNG 647. Points (A) and (B) correspond to phase offsets of .+-.1 bit, respectively. A point (C) corresponds to the regular phase, and is a sync capture point.
As there is a difference between the clock of the PNG 647 and the regular clock, a point where both phases coincide with each other appears at an interval corresponding to this difference. If the phase of the spread code generated in the PNG 647 is identical with that of the regular spread code P(t), the despreading operation is carried out. And, the mixer 603 generates an angle-modulated signal fi(t). The reproduction of the carrier is done in the carrier reproduction circuit 650. As a result, the demodulation output increases abruptly. FIG. 18 shows the steep increase in the level of the demodulation output, maximum value of which is obtained at time t0.
The threshold level detector 634 detects this steep increase, by comparing the demodulation output with a predetermined threshold value (SHL). On the basis of this detection, the threshold level detector 634 outputs a control signal to a shaping circuit 635, which generates a direct current which gives a frequency offset to the VCO 621. This direct current is added with the control signal of the DLL-type sync capture circuit 636 in the adder 642. The clock supplied to the PNG 647 is then equalized to the regular clock. The synchronous condition is thus caught up. After that, the demodulation apparatus repeats the steady operation.
In this synchronous SS modulation/demodulation system, as is explained in the foregoing description, the synchronous time detection fairly depends on a signal level. Therefore, the AGC 602 is definitely necessary. Furthermore, two VCO control loops are also necessary. Thus, the circuit tends to be complicate.